1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as an electrically erasable and programmable read only memory (EEPROM), and more particularly, to a nonvolatile semiconductor device including memory cells each having a split gate for compensating for an over-erasing operation.
2. Description of the Related Art
Generally, an EEPROM cell includes a P-type semiconductor substrate having an N.sup.+ -type source region and an N.sup.+ -type drain region, a floating gate via an insulating layer on the semiconductor substrate between the source region and the drain region, and a control gate via another insulating layer on the floating gate. In a write mode, a high positive voltage is applied to the drain region and another high positive voltage is applied to the control gate, while the source region is grounded. As a result, hot electrons having an energy larger than an energy barrier of the insulating layer between the floating gate and the semiconductor substrate are introduced into the floating gate, thus completing a writing operation. In this case, the threshold voltage of the EEPROM cell is made higher. On the other hand, in an erase mode, the source region is in a floating state, a positive voltage is applied to the drain region, the substrate is grounded, and a negative voltage (or the ground potential) is applied to the control gate. As a result, the electrons stored in the floating gate are extracted thereform to the drain region utilizing the Fowler-Nordheim tunneling effect. To realize the Fowler-Nordheim tunneling effect, the insulating layers are made very thin.
In the above-mentioned erase mode, however, when more electrons than those introduced in a write mode are extracted from the floating gate, the threshold voltage of the EEPROM cell may be made negative, i.e., the EEPROM cell becomes a depletion type transistor. Such an erasing operation is called an over-erasing operation.
In order to compensate for such an over-erasing operation, there has been known an EEPROM cell having a split gate (see JP-A-2-23672). In this prior art EEPROM cell, an offset length between the floating gate and the source region is determined in self-alignment with the floating gate, to precisely adjust the channel length, the ratio of coupled capacitance of the control gate to the floating gate and the cell area. This will be explained later in detail.
In the above-described prior art EEPROM cell, however, since the ratio of coupled capacitance of the control gate to the floating gate is decreased, the controllability of the control gate to the floating gate is deteriorated. Also, if a channel region is not in alignment with the control gate, the controllability of the control gate is deteriorated. As a result, the efficiency of introducing hot electrons into the floating gate in a write mode, the efficiency of extracting electrons from the floating gate in a read mode, and a read current are reduced.
Further, the above-described prior art EEPROM cell is disadvantageous in terms of integration.